A. Technical Field
The present invention relates generally to oscilloscopes, and more particularly, to user interfaces, methods, and systems for measuring and representing values in signal measurement systems.
B. Background of the Invention
Double data rate (DDR) memory technology has become more prevalent in the marketplace, and includes the capability of clocking data on both rising and falling edges of a strobe signal in a memory interface. Similarly, the next generation DDR2 technology has provided an additional two-times improvement in bandwidth over its DDR predecessor by doubling the maximum clock frequency.
With any high-speed interface, as the operating frequencies increase, it becomes progressively more difficult to meet the signal integrity and timing requirements at the receivers. With tighter timing budgets, signals tend to deteriorate because faster edge rates are needed to meet them. As edge rates get faster, effects like overshoot, reflections, and crosstalk become more significant problems on the interface resulting in a negative impact on the timing budget. A significant change incorporated into next generations of DDR technology to counter the impact on the timing budget is signal slew rate de-rating for both data and address/command signals.
One challenging aspect of the memory interface designers is to meet the setup and hold time requirements of the receivers. The setup and hold time values vary depending on the input signal slew rate. In order to compute slew rate properly, a user needs to know how to measure signal slew rate, and how to make use of Joint Electron Device Engineering Council (JEDEC) specified de-rating tables.
In DDR2 technology, the typical definition for the setup and hold time for memory components is 1.0 Volt/nano-second (V/ns) input slew rate. By design, slew rate of a memory chip can be faster or slower. Accordingly, the setup and hold time requirements are changed, since the user cannot use the same slew rate of 1.0 V/ns. This discrepancy has led to the need for slew rate de-rating on the signals specific to user design.
Conventional attempts at solving these challenges implement a series of manual steps, including manual measurements, which are cumbersome and challenging to complete.
The following steps are an example of a typical approach. First, the slew rate on the input signal is measured. This is done by finding nominal slew rate of the signal in the transition region between the specified voltage levels. The nominal method and voltage levels are defined in the JEDEC DDR2 and DDR3 specifications. Second, a determination is made whether the region of interest of the signal needs to use the nominal or the tangent method. The tangent method is used if signal transition results in a slope greater than the nominal line at the switching region. Tangent method is also defined in the JEDEC DDR2 and DDR3 specifications. It is time consuming to detect the slopes and then decide on which method to use as the slope has to be calculated for each sample point from the reference level between the two voltage levels. According to the specification, it has to be ensured that the slope occurring due to tangent should be earlier than the nominal line.
Next, slew rate on both rise and fall slopes for all the acquired transitions is computed. The cycle-by-cycle slew should be calculated to know the worst case behavior of the device under test (DUT), which is tedious to perform on rise and fall slopes, particularly when the acquired signal duration is long enough to accommodate hundreds of cycles. Meanwhile, the correct relationship between the polarity of the de-rating value and the direction of margin impact must be maintained. Thereafter, the slew rate on two separate signals is computed. A user makes use of the two typical slew rate values to index the appropriate de-rating table. The JEDEC specifies different tables for the different speeds to obtain the delta value. Finally, the delta value is added to the limits taken from the data sheet of the base measurement, which represents the de-rated limits.
Thus, the designers of high speed communication technologies need to perform various and laborious calculations of the limits to understand the dynamic behavior of the system. Moreover, with the emergence of DDR memory technologies, the measurements which were static needed to be calculated over and over again by a designer to get a deeper understanding of the behavior of the system in hand. Further, such manual measurements are error prone.
Therefore, a need remains for an improved solution where a designer can easily carry out various calculations of the limits to understand the dynamic behavior of the system.